Embedded-chip packaging is a semiconductor chip (die) packaging technology where materials are added to a printed circuit structure to create optional passive elements such as resistors and capacitors, and active chips (dies) are placed on an internal layer and then buried as additional layers are added. For example some embedded-chip processes include die placement with non-conductive paste attach to a pre-patterned Cu foil, lamination of standard glass reinforced, prepreg (pre-impregnated composite fibers where a matrix material, such as epoxy, is already present) for dimensional stability, and Cu foil patterning to realize PCB (printed circuit board) routing layers. Typical laminate structures can be two to six layers with more complex structures being up to ten metal layers. Standard packaging processes such as wire or clip bonding, as well as common molding techniques, are typically replaced with galvanic processes. The results are a significantly reduced package footprint, package resistance and inductance, as well as low thermal resistance. However, it would be desirable to optimize embedded-chip packaging technologies for multi-chip assemblies so that the embedded-chip packaging technologies are adapted and expanded to meet the needs of different chip technologies e.g. such as high power contacts for power semiconductor dies and dies of different thickness embedded in the same package.